1. Field of the Invention
The present invention relates to a wafer and a method of manufacturing a semiconductor device. In particular, the present invention relates to a wafer to be diced into a plurality of chips and a method of manufacturing a semiconductor device including a process of dicing a wafer into a plurality of chips.
2. Description of Related Art
Typically, a plurality of chip regions are formed on a semiconductor wafer. The respective chip regions are separated from each other by dicing streets. The dicing is carried out by cutting the semiconductor wafer along the dicing streets by using a dicing blade. It is known that in the dicing process, chipping of the semiconductor wafer may be caused on the cut surface, because the semiconductor wafer is physically cut by the blade.
Meanwhile, in the dicing process, a surface of the semiconductor wafer is typically covered by polyimide resin and the like for protecting the surface. A method for suppressing the occurrence of the chipping by using the polyimide resin is disclosed, for example, in Patent Document 1 (Japanese Patent Publication JP-2003-203882). According to the method, the chipping is suppressed by covering a surface of a region of the semiconductor wafer to be cut by the blade with the polyimide resin,
FIG. 1 is a cross-sectional view of a compound semiconductor substrate 111 used in the above-described manufacturing method. A plurality of semiconductor device formation regions 112 are provided on a top surface of the compound semiconductor substrate 111, and a dicing region 114 is provided between the plurality of semiconductor device formation regions 112. Polyimide films 116 as protection films are formed on respective surfaces of the semiconductor device formation region 112 and the dicing region 114. A space is provided between the polyimide film 116 of the dicing region 114 and the polyimide film 116 of the semiconductor device formation region 112. As shown in FIG. 2, the compound semiconductor substrate 111 is cut along the dicing region 114. Film stress is generated at stress change points 119 corresponding to side edges t of the polyimide films 116, and stress in the compound semiconductor substrate 111 is changed due to the film stress of the polyimide film 116. As a result, crack generated at the cut point of the compound semiconductor substrate 111 due to the dicing stops at the stress change point 119 and does not intrude into the semiconductor device formation region 112. It is thus possible to suppress the occurrence of the chipping on the diced chip. It should be noted that Patent Document 2 (Japanese Patent Publication JP-2008-28243) discloses a technique of forming an anti-chipping wall by using a metal interconnection for preventing the chipping.
The inventor of the present application has recognized the following points. According to the technique described in FIGS. 1 and 2, the polyimide resin as well as the semiconductor wafer is cut by the blade and thus the polyimide resin in filaments is attached as shaving to the cut surface of the semiconductor wafer.